LTC4210-2CS6#TRM【PDF 11/20 页】IC CONTROLLER HOT SWAP TSOT23-6

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LTC4210-1/LTC4210-2

421012f

Whichever method of compensation is used, board level

short-circuit testing is highly recommended as board

layout can affect transient performance. Beside frequency

compensation, the total gate capacitance C

GATE

also

determines the GATE start-up as in Equation 6. The C

GATE

should be kept below 0.15礔 at high supply operation as

the capacitive energy ( 0.5 " C

GATE

" V

GATE

) is discharged

by the LTC4210 internal pull-down transistor. This pre-

vents the internal pull-down transistor from overheating

when the GATE turns off and/or is servoing during current

limiting.

Timer Function

The TIMER pin handles several key functions with an

external capacitor, C

TIMER

. There are two comparator

thresholds: COMP1 (0.2V) and COMP2 (1.3V). The four

timing current sources are:

5礎 pull-up

60礎 pull-up

2礎 pull-down

100礎 pull-down

The 100礎 is a nonideal current source approximating a

7k resistor below 0.4V.

Initial Timing Cycle

When the card is being inserted into the bus connector, the

long pins mate first which brings up the supply V

at time

point 1 of Figure 3. The LTC4210 is in reset mode as the

ON pin is low. GATE is pulled low and the TIMER pin is

pulled low with a 100礎 source. At time point 2, the short

pin makes contact and ON is pulled high. At this instant, a

start-up check requires that the supply voltage be above

UVLO, the ON pin be above 1.3V and the TIMER pin voltage

be less than 0.2V. When these three conditions are ful-

filled, the initial cycle begins and the TIMER pin is pulled

high with 5礎. At time point 3, the TIMER reaches the

COMP2 threshold and the first portion of the initial cycle

ends. The 100礎 current source then pulls down the

TIMER pin until it reaches 0.2V at time point 4. The initial

cycle delay (time point 2 to time point 4) is related to

TIMER

by equation:

INITIAL

H 272.9 " C

TIMER

ms/礔

(5)

When the initial cycle terminates, a start-up cycle is

activated and the GATE pin ramps high. The TIMER pin

continues to be pulled down towards ground.

APPLICATIO S I FOR ATIO

>2.5V

COMP2

100礎

10礎

GATE

RESET

MODE

OUT

TIMER

3 4 5

COMP1

4210 F03

5礎

INITIAL

CYCLE

START-UP

CYCLE

NORMAL

CYCLE

DISCHARGE

BY LOAD

>1.3V

Figure 3. Normal Operating Sequence

Start-Up Cycle Without Current Limit

The GATE is released with a 10礎 pull-up at time point 4

of Figure 3. At time point 5, GATE reaches the external

MOSFET threshold V

and V

OUT

starts to follow the GATE

ramp up. If the R

SENSE

current is below the current limit,

the GATE ramps at a constant rate of:

GATE

(6)

where C

GATE

is the total capacitance at the GATE pin.

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